x86: remove duplicated IA32_FEATURE_CONTROL MSR macro

Below commit introduced a new macro MSR_IA32_FEATURE_CONTROL for
IA32_FEATURE_CONTROL MSR but it didn't remove old IA32_FEATURE_CONTROL_MSR
macro. The new one has better naming convention, so remove the old as a
duplication. Also move the macros of bit definition of IA32_FEATURE_CONTROL MSR
down to make them together with the new one. The *_MSR* infix is also removed as
it is pointless.

commit 5a211704e8813c4890c8ce8dc4189d1dfb35ecd0
Author: Len Brown <len.brown@intel.com>
Date:   Fri Apr 8 22:31:47 2016 +0200

    mwait-idle: prevent SKL-H boot failure when C8+C9+C10 enabled

    Some SKL-H configurations require "max_cstate=7" to boot.
    While that is an effective workaround, it disables C10.

    ......

Above commit also used SGX_ENABLE (bit 18) in IA32_FEATURE_CONTROL MSR without a
macro for it. A new macro IA32_FEATURE_CONTROL_SGX_ENABLE is also added for
better code and future use.

Relevant code that uses those macros are changed accordingly.

Signed-off-by: Kai Huang <kai.huang@linux.intel.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Kevin Tian <kevin.tian@intel.com>

diff --git a/xen/arch/x86/cpu/mwait-idle.c b/xen/arch/x86/cpu/mwait-idle.c
index e062e2139f92fbd98a86908081df577089737028..4b339747745bd4bc6345c07b9e0e765e865c7f57 100644 (file)
--- a/xen/arch/x86/cpu/mwait-idle.c
+++ b/xen/arch/x86/cpu/mwait-idle.c
@@ -1006,7 +1006,7 @@ static void __init sklh_idle_state_table_update(void)
                rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
 
                /* if SGX is enabled */
-               if (msr & (1 << 18))
+               if (msr & IA32_FEATURE_CONTROL_SGX_ENABLE)
                        return;
        }
 

diff --git a/xen/arch/x86/hvm/vmx/vmcs.c b/xen/arch/x86/hvm/vmx/vmcs.c
index 848ac335a52283d94775fce67dc80fed9f2d85d0..46b63b60f66de5d34d4dc68df406ce69a5e1dd21 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vmcs.c
+++ b/xen/arch/x86/hvm/vmx/vmcs.c
@@ -604,14 +604,14 @@ int vmx_cpu_up(void)
         return -EINVAL;
     }
 
-    rdmsr(IA32_FEATURE_CONTROL_MSR, eax, edx);
+    rdmsr(MSR_IA32_FEATURE_CONTROL, eax, edx);
 
-    bios_locked = !!(eax & IA32_FEATURE_CONTROL_MSR_LOCK);
+    bios_locked = !!(eax & IA32_FEATURE_CONTROL_LOCK);
     if ( bios_locked )
     {
         if ( !(eax & (tboot_in_measured_env()
-                      ? IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX
-                      : IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX)) )
+                      ? IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX
+                      : IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX)) )
         {
             printk("CPU%d: VMX disabled by BIOS.\n", cpu);
             return -EINVAL;
@@ -619,11 +619,11 @@ int vmx_cpu_up(void)
     }
     else
     {
-        eax  = IA32_FEATURE_CONTROL_MSR_LOCK;
-        eax |= IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX;
+        eax  = IA32_FEATURE_CONTROL_LOCK;
+        eax |= IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX;
         if ( test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability) )
-            eax |= IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX;
-        wrmsr(IA32_FEATURE_CONTROL_MSR, eax, 0);
+            eax |= IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX;
+        wrmsr(MSR_IA32_FEATURE_CONTROL, eax, 0);
     }
 
     if ( (rc = vmx_init_vmcs_config()) != 0 )
@@ -639,8 +639,8 @@ int vmx_cpu_up(void)
     case -2: /* #UD or #GP */
         if ( bios_locked &&
              test_bit(X86_FEATURE_SMX, &boot_cpu_data.x86_capability) &&
-             (!(eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX) ||
-              !(eax & IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX)) )
+             (!(eax & IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX) ||
+              !(eax & IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX)) )
         {
             printk("CPU%d: VMXON failed: perhaps because of TXT settings "
                    "in your BIOS configuration?\n", cpu);

diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c
index 9d4121ef1257702b57381dbb9cccccf9d118d980..a0f579348654f54b7a03549f9dc4ca49298964b1 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vmx.c
+++ b/xen/arch/x86/hvm/vmx/vmx.c
@@ -2622,7 +2622,7 @@ static int vmx_msr_read_intercept(unsigned int msr, uint64_t *msr_content)
     case MSR_IA32_DEBUGCTLMSR:
         __vmread(GUEST_IA32_DEBUGCTL, msr_content);
         break;
-    case IA32_FEATURE_CONTROL_MSR:
+    case MSR_IA32_FEATURE_CONTROL:
     case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_VMFUNC:
         if ( !nvmx_msr_read_intercept(msr, msr_content) )
             goto gp_fault;
@@ -2848,7 +2848,7 @@ static int vmx_msr_write_intercept(unsigned int msr, uint64_t msr_content)
 
         break;
     }
-    case IA32_FEATURE_CONTROL_MSR:
+    case MSR_IA32_FEATURE_CONTROL:
     case MSR_IA32_VMX_BASIC...MSR_IA32_VMX_TRUE_ENTRY_CTLS:
         if ( !nvmx_msr_write_intercept(msr, msr_content) )
             goto gp_fault;

diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index c6a39e98cb43b99ce0194eff28b7ed25649a1499..bed2e0a360ed3efe331310b6447fae6888de25c1 100644 (file)
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -1941,9 +1941,9 @@ int nvmx_msr_read_intercept(unsigned int msr, u64 *msr_content)
         data = gen_vmx_msr(data, VMX_ENTRY_CTLS_DEFAULT1, host_data);
         break;
 
-    case IA32_FEATURE_CONTROL_MSR:
-        data = IA32_FEATURE_CONTROL_MSR_LOCK | 
-               IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX;
+    case MSR_IA32_FEATURE_CONTROL:
+        data = IA32_FEATURE_CONTROL_LOCK |
+               IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX;
         break;
     case MSR_IA32_VMX_VMCS_ENUM:
         /* The max index of VVMCS encoding is 0x1f. */

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index e0f7f8d51d97160dd637b8471f1a7f8a3d8ac11b..6098f133ebf2339112aae282d1bb7d8fcbc9c294 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -133,12 +133,6 @@
 #define MSR_IA32_VMX_TRUE_EXIT_CTLS             0x48f
 #define MSR_IA32_VMX_TRUE_ENTRY_CTLS            0x490
 #define MSR_IA32_VMX_VMFUNC                     0x491
-#define IA32_FEATURE_CONTROL_MSR                0x3a
-#define IA32_FEATURE_CONTROL_MSR_LOCK                     0x0001
-#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_INSIDE_SMX  0x0002
-#define IA32_FEATURE_CONTROL_MSR_ENABLE_VMXON_OUTSIDE_SMX 0x0004
-#define IA32_FEATURE_CONTROL_MSR_SENTER_PARAM_CTL         0x7f00
-#define IA32_FEATURE_CONTROL_MSR_ENABLE_SENTER            0x8000
 
 /* K7/K8 MSRs. Not complete. See the architecture manual for a more
    complete list. */
@@ -288,7 +282,15 @@
 #define MSR_IA32_PLATFORM_ID           0x00000017
 #define MSR_IA32_EBL_CR_POWERON                0x0000002a
 #define MSR_IA32_EBC_FREQUENCY_ID      0x0000002c
+
 #define MSR_IA32_FEATURE_CONTROL       0x0000003a
+#define IA32_FEATURE_CONTROL_LOCK                     0x0001
+#define IA32_FEATURE_CONTROL_ENABLE_VMXON_INSIDE_SMX  0x0002
+#define IA32_FEATURE_CONTROL_ENABLE_VMXON_OUTSIDE_SMX 0x0004
+#define IA32_FEATURE_CONTROL_SENTER_PARAM_CTL         0x7f00
+#define IA32_FEATURE_CONTROL_ENABLE_SENTER            0x8000
+#define IA32_FEATURE_CONTROL_SGX_ENABLE               0x40000
+
 #define MSR_IA32_TSC_ADJUST            0x0000003b
 
 #define MSR_IA32_APICBASE              0x0000001b